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IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
2 ______________________________________________________________________________________
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
V
DD
 to V
SS
 ..........................................................-0.3V to +100V
DET, RTN, WAD, PG, 2EC to V
SS .......................
-0.3V to +100V
CLS to V
SS
 ..............................................................-0.3V to +6V
Maximum Current on CLS (100ms maximum) .................100mA
Continuous Power Dissipation (T
A
 = +70NC) (Note 1)
   TQFN (derate 28.6mW/NC above +70NC)
   Multilayer Board .....................................................2285.7mW
Operating Temperature Range ..........................-40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................-65NC to +150NC
Lead Temperature (soldering, 10s) .............................. +300NC
Soldering Temperature ................................................. +260NC
ELECTRICAL CHARACTERISTICS
(V
IN
 = (V
DD
 - V
SS
) = 48V, R
DET
 = 24.9k? R
CLS
 = 615? and R
SL
 = 60.4k? RTN, WAD, PG, and 2EC unconnected, all voltages are
referenced to V
SS,
 unless otherwise noted. T
A
 = T
J
 = -40NC to +85NC, unless otherwise noted. Typical values are at T
A
 = +25NC.)
(Note 3)
ABSOLUTE MAXIMUM RATINGS
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
TQFN
Junction-to-Ambient Thermal Resistance (B
JA)
  ..............35NC/W
Junction-to-Case Thermal Resistance (B
JC)
 .................2.7NC/W
PACKAGE THERMAL CHARACTERISTICS (Note 2)
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DETECTION MODE
Input Offset Current
I
OFFSET
V
IN
 = 1.4V to 10.1V (Note 4)
10
FA
Effective Differential Input
Resistance
dR
V
IN
 = 1.4V up to 10.1V with 1V step,
V
DD
= RTN = WAD = PG = 2EC (Note 5)
23.95
25.00
25.50
kI
CLASSIFICATION MODE
Classification Disable
Threshold
V
TH,CLS
V
IN
rising (Note 6)
22.0
22.8
23.6
V
Classification Stability Time
0.2
ms
Classification Current
I
CLASS
V
IN
 = 12.5V to
20.5V, V
DD
=
RTN = WAD =
PG = 2EC
Class 0, R
CLS
 = 619I
0
3.96
mA
Class 1, R
CLS
 = 117I
9.12
11.88
Class 2, R
CLS
 = 66.5I
17.2
19.8
Class 3, R
CLS
 = 43.7I
26.3
29.7
Class 4, R
CLS
 = 30.9I
36.4
43.6
Class 5, R
CLS
 = 21.3I
52.7
63.3
TYPE 2 (802.3at) CLASSIFICATION MODE
Mark Event Threshold
V
THM
V
IN
 falling
10.1
10.7
11.6
V
Hysteresis on Mark Event
Threshold
0.84
V
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